1. Field of the Invention
The present invention relates to a power semiconductor device and a method for fabricating the same, and more particularly, to a power semiconductor device having a source structure of a narrow radius of curvature and a high breakdown voltage and a method for fabricating the same.
2. Description of the Related Art
In a power semiconductor device, a radius of curvature of a source region or a drain region has a close relation with a breakdown voltage of a device. In particular, the radius of curvature of the source region which is relatively small, is one of main causes for decreasing the breakdown voltage of the device. As well known, this is the reason why a field crowding phenomenon occurs in a junction of a narrow radius of curvature.
FIG. 1 is a lay-out view of a conventional power semiconductor device, for example, a field effect transistor (FET). FIG. 2 is a sectional view taken along line II-IIxe2x80x2 of FIG. 1. Same reference numerals in FIGS. 1 and 2 denote the same region or layer.
As shown in FIGS. 1 and 2, a conventional FET 1 includes a source structure 10 having a line segment-shaped projected portion 10xe2x80x2 on its center, formed so as to surround a predetermined region of right and left and upper portions of the projected portion 10xe2x80x2. The FET 1 includes a drain structure 20 formed so as to surround the projected portion 10xe2x80x2 of the source structure 10 in a region surrounded by the source structure 10. The drain structure 20 is spaced-apart from the source structure 10.
The source structure 10 includes a source electrode 11 on the surface of a semiconductor substrate 2, a region of first conductivity type impurities, for example, a p-type well region 12 formed in the semiconductor substrate 2 under the source electrode 11, and a region having a high concentration of second conductivity type impurities, for example, a n+-type source region 13, and a region having a high concentration of first conductivity type impurities, for example, a p+-type region 14, which are formed under the surface of the p-type well region 12.
The drain structure 20 includes a drain electrode 21 on the surface of the semiconductor substrate 2 and a n-type well region 22 formed in the semiconductor substrate 2 under the drain electrode 21. The n-type well region 22, as known from a sectional structure of FIG. 2, is connected to an extended drain structure 23 of a second conductivity type which is not surrounded by the drain electrode 21. The drain structure 20 also includes a n+-type drain region 24 formed under the surface of the n-type well region 22. The extended drain structure 23 includes a p-type top region 25 formed under the surface of the n-type well region 22.
A gate electrode 30 is formed so as to be insulated from a channel region by a gate dielectric layer 40. The source electrode 11, the drain electrode 21, and the gate electrode 30 are insulated one another by an interdielectric layer 50.
In the conventional FET, a channel is uniformly formed between the source structure 10 and the drain structure 20. Thus, a channel current is nearly uniformly distributed. In this case, a breakdown current is generated by the field crowding phenomenon in a tip 10t of the projected portion 10xe2x80x2 of the source structure 10. To prevent the phenomenon, a radius of curvature of the tip 10t must be increased, however, in that case, the area of the transistor is increased.
To solve the above problems, it is an object of the present invention to provide a power semiconductor device having a source structure of a small radius of curvature and a small area of a transistor and a high breakdown voltage.
It is another object of the present invention to provide a method for fabricating the power semiconductor device.
Accordingly, to achieve the above object, there is provided a power semiconductor device. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center, formed so as to surround a predetermined region of right and left and upper portions of the projected portion, and containing a source electrode formed so as to contact extended regions of first and second conductivity types with high concentration in a well region of a first conductivity type, drain structures formed so that two drain structures are separated each other in a predetermined region surrounded by the source structure and each of the two drain structures is spaced-apart from the side of the projected portion of the source structure and does not exist on the end portion of the projected portion, and containing a drain electrode formed so as to contact an extended region of a second conductivity type with high concentration in a well region of a second conductivity type, extended drain structures formed so as to be connected to the well region of a second conductivity type and extend from the drain structures to a predetermined distance, and forming a channel with a field effect channel between sides of the projected portion of the source structure and the extended drain structures, and not forming a channel in an upper portion of the projected portion of the source structure, and a gate structure arranged on the field effect channel between the source structure and the extended drain structures.
Preferably, the extended drain structures contain the extended well region of the second conductivity type connected to the second conductivity type well region and a top region of a first conductivity type formed under the surface of the extended well region of the second conductivity type.
Preferably, the drain structures are connected to the drain electrode in an adjacent drain structure.
In order to achieve another object, there is provided a method for fabricating a power semiconductor device. The method comprises the steps of: forming so that two well regions of a second conductivity type under the surface of a semiconductor substrate of a first conductivity type are spaced-apart from each other; forming a well region of a first conductivity type so as to surround the well region of a second conductivity type, and having a projected portion with a tip-shaped end portion so as to be in line with the well regions of a second conductivity type between adjacent well regions of a second conductivity type; forming drain and source regions of a second conductivity type with high concentration, respectively, in the well regions of a second conductivity type and a first conductivity type; forming a gate dielectric layer on the surface of the semiconductor substrate between the well regions of a second conductivity type and a first conductivity type; forming a gate electrode on the gate dielectric layer; forming a drain electrode on the drain region of a second conductivity type with high concentration; and forming a source electrode on the source region of a second conductivity type with high concentration.
The method further comprises the step of forming a top region of a first conductivity type around the drain region in the well region of a second conductivity type.
The method further comprises the step of forming a first conductive region with high concentration so as to be adjacent to the source region in the well region of a first conductivity type.
Preferably, the drain electrode is formed so as to connect adjacent drain electrodes each other.